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advance information 1-mbit (128k x 8) nvsram cy14b101l cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-06400 rev. *a revised february 22, 2006 features ? 25 ns, 35 ns, and 45 ns access times ? ?hands-off? automatic store on power-down with only a small capacitor ? store to quantumtrap? nonvolatile elements is initiated by software, device pin or autostore? on power-down ? recall to sram initiated by software or power-up ? unlimited read, write and recall cycles ? 5 ma typical i cc at 200-ns cycle time ? 1,000,000 store cycles to quantumtrap ? 100-year data retention ? single 3v operation +20%, -10% ? commercial and industrial temperature ? soic and ssop packages ?rohs compliance functional description the cypress cy14b101l is a fast static ram with a nonvol- atile element in each memory cell. the embedded nonvolatile elements incorporate quantumtrap technology producing the world?s most reliable nonvolat ile memory. the sram provides unlimited read and write cycles, while independent, nonvolatile data resides in the highly reliable quantumtrap cell. data transfers from the sram to the nonvolatile elements (the store operation) takes place automatically at power-down. on power-up, data is restored to the sram (the recall operation) from the nonvolatile memory. both the store and recall operations are also available under software control. logic block diagram ce we oe
advance information cy14b101l document #: 001-06400 rev. *a page 2 of 17 pin configurations a 16 nc dq7 dq6 dq5 nc dq4 v cc dq3 dq2 dq1 dq0 v ss a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 nc hsb we nc nc a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 48-ssop top view (not to scale) oe ce v cc v ss v cap nc nc nc nc nc nc nc nc nc 32-lead soic ce oe we
advance information cy14b101l document #: 001-06400 rev. *a page 3 of 17 device operation the cy14b101l nvsram is made up of two functional components paired in the same physical cell. these are a sram memory cell and a nonvolatile quantumtrap cell. the sram memory cell operates as a standard fast static ram. data in the sram can be transferred to the nonvolatile cell (the store operation), or from the nonvolatile cell to sram (the recall operation). this unique architecture allows all cells to be stored and recalled in parallel. during the store and recall operations sram read and write operations are inhibited. the cy14b101l supports unlimited reads and writes just like a typical sram. in addition, it provides unlimited recall operations from the nonvolatile cells and up to 1 million store operations. sram read the cy14b101l performs a read cycle whenever ce and oe are low while we and hsb are high. the address specified on pins a 0-16 determines which of the 131,072 data bytes will be accessed. when the read is initiated by an address transition, the outputs will be valid after a delay of t aa (read cycle #1). if the read is initiated by ce or oe , the outputs will be valid at t ace or at t doe , whichever is later (read cycle #2). the data outputs will repeatedly respond to address changes within the t aa access time without the need for transitions on any control input pins, and will remain valid until another address change or until ce or oe is brought high, or we or hsb is brought low. sram write a write cycle is performed whenever ce and we are low and hsb is high. the address inputs must be stable prior to entering the write cycle and must remain stable until either ce or we goes high at the end of the cycle. the data on the common i/o pins i/o 0?7 will be written into the memory if it is valid t sd before the end of a we controlled write or before the end of an ce controlled write. it is recommended that oe be kept high during the entire write cycle to avoid data bus contention on common i/o lines. if oe is left low, internal circuitry will turn off the output buffers t hzwe after we goes low. autostore? operation the cy14b101l stores data to nvsram using one of three storage operations. these th ree operations are hardware store, activated by hsb , software store, activated by an address sequence, and autostore, on device power-down. autostore operation is a un ique feature of quantumtrap technology and is enabled by default on the cy14b101l. during normal operation, the device will draw current from v cc to charge a capacitor connected to the v cap pin. this stored charge will be used by the chip to perform a single store operation. if the voltage on the v cc pin drops below v switch , the part will automatica lly disconnect the v cap pin from v cc . a store operation will be initiated with power provided by the v cap capacitor. figure 1 shows the proper connecti on of the storage capacitor (v cap ) for automatic store operatio n. refer to the dc charac- teristics table for the size of v cap . the voltage on the v cap pin is driven to 5v by a charge pump internal to the chip. a pull-up should be placed on we to hold it inactive during power-up. to reduce unnecessary nonvolatile stores, autostore and hardware store operations will be ignored unless at least one write operation has taken place since the most recent store or recall cycle. so ftware initiated store cycles are performed regardless of whether a write operation has taken place. the hsb signal can be monitored by the system to detect an autostore cycle is in progress. hardware store (hsb) operation the cy14b101l provides the hsb pin for controlling and acknowledging the store operations. the hsb pin can be used to request a hardware store cycle. when the hsb pin is driven low, the cy14b101l will conditionally initiate a store operation after t delay . an actual store cycle will only begin if a write to the sram took place since the last pin definitions pin name i/o type description a 0 ?a 16 input address inputs used to select one of the 131,072 bytes of the nvsram . dq0-dq7 input/output bidirectional data i/o lines . used as input or output lines depending on operation. we input write enable input, active low . when selected low, enables data on the i/o pins to be written to the address location latched by the falling edge of ce . ce input chip enable input, active low . when low, selects the chip. when high, deselects the chip. oe input output enable, active low . the active low oe input enables the data output buffers during read cycles. deasserting oe high causes the i/o pins to tri-state. v ss ground ground for the device. should be connected to ground of the system. v cc power supply power supply inputs to the device . hsb input/output hardware store busy . when low this output indicates a hardware store is in progress. when pulled low external to the chip it will initiate a nonvolatile store operation. a weak internal pull up resistor keeps this pin high if not connected. (connection optional) v cap power supply autostore capacitor . supplies power to nvsram during power loss to store data from sram to nonvolatile elements. nc no connect no connects . this pin is not connected to the die.
advance information cy14b101l document #: 001-06400 rev. *a page 4 of 17 store or recall cycle. the hsb pin also acts as an open drain driver that is internally driven low to indicate a busy condition while the store (initiated by any means) is in progress. sram read and write operations that are in progress when hsb is driven low by any means are given time to complete before the store operation is initiated. after hsb goes low, the cy14b101l will co ntinue sram operations for t delay . during t delay , multiple sram read operations may take place. if a write is in progress when hsb is pulled low it will be allowed a time, t delay , to complete. however, any sram write cycles requested after hsb goes low will be inhibited until hsb returns high. during any store operation, regardless of how it was initiated, the cy14b101l will continue to drive the hsb pin low, releasing it only when the store is complete. upon completion of the store operation the cy14b101l will remain disabled until the hsb pin returns high. if hsb is not used, it should be left unconnected. hardware recall (power-up) during power-up, or after any low-power condition (v cc < v switch ), an internal recall request will be latched. when v cc once again exceeds the sense voltage of v switch , a recall cycle will automatically be initiated and will take t hrecall to complete. software store data can be transferred from the sram to the nonvolatile memory by a software address sequence. the cy14b101l software store cycle is init iated by executing sequential ce -controlled read cycles from six specific address locations in exact order. during the store cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. once a store cycle is initiated, further i nput and output are disa bled until the cycle is completed. because a sequence of reads from specific addresses is used for store initiation, it is important that no other read or write accesses intervene in the sequence, or the sequence will be aborted and no store or recall will take place. to initiate the software store cycle, the following read sequence must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x8fc0 initiate store cycle the software sequence may be clocked with ce controlled reads or oe controlled reads. once the sixth address in the sequence has been entered, the store cycle will commence and the chip wi ll be disabled. it is important that read cycles and not write cycles be used in the sequence, although it is not necessary that oe be low for the sequence to be valid. after the t store cycle time has been fulfilled, the sram will again be activated for read and write operation. software recall data can be transferred from the nonvolatile memory to the sram by a software address sequence. a software recall cycle is initiated with a sequence of read operations in a manner similar to the software store initiation. to initiate the recall cycle, the following sequence of ce controlled read operations must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x4c63 initiate recall cycle internally, recall is a two-step procedure. first, the sram data is cleared, and second , the nonvolatile information is transferred into the sr am cells. after the t recall cycle time the sram will once again be ready for read and write operations. the recall operation in no way alters the data in the nonvolatile elements. figure 1. autostore tm mode we
advance information cy14b101l document #: 001-06400 rev. *a page 5 of 17 preventing autostore the autostore function can be disabled by initiating an autostore disable sequence. a sequence of read operations is performed in a manner similar to the software store initi- ation. to initiate the autostore disable sequence, the following sequence of ce -controlled read operations must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x8b45 autostore disable the autostore can be re-enabled by initiating an autostore enable sequence. a sequence of read operations is performed in a manner similar to the software recall initi- ation. to initiate the autostore enable sequence, the following sequence of ce -controlled read operations must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x4b46 autostore enable if the autostore function is disabled or re-enabled, a manual store operation (hardware or software) needs to be issued to save the autostore state through subsequent power down cycles. the part comes from the factory with autostore enabled. data protection the cy14b101l protects data from corruption during low-voltage conditions by inhibiting all externally initiated store and write operations. the low voltage condition is detected when v cc < v switch . if the cy14b101l is in a write mode (both ce and we low) at power-up, after a recall, or after a store, the write will be inhibited until a negative transition on ce or we is detected. this protects notes: 1. the six consecutive address locations must be in the order listed. we must be high during all six cycles to enable a non-volatile cycle. 2. while there are 17 address lines on the cy14b101l, only the lower 16 lines are used to control software modes. 3. i/o state depends on the state of oe . the i/o table shown assumes oe low. table 1. mode selection ce we oe a15 - a0 mode i/o power h x x x not selected output high z standby l h l x read sram output data active l l x x write sram input data active l h l 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x8b45 read sram read sram read sram read sram read sram autostore disable output data output data output data output data output data output data active [1,2,3] l h l 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x4b46 read sram read sram read sram read sram read sram autostore enable output data output data output data output data output data output data active [1,2,3] l h l 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x8fc0 read sram read sram read sram read sram read sram nonvolatile store output data output data output data output data output data output high z active i cc2 [1,2,3] l h l 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x4c63 read sram read sram read sram read sram read sram nonvolatile recall output data output data output data output data output data output high z active [1,2,3]
advance information cy14b101l document #: 001-06400 rev. *a page 6 of 17 against inadvertent writes during power-up or brown-out conditions. noise considerations the cy14b101l is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1 f connected between v cc and v ss , using leads and traces that are as short as possible. as with all high-speed cmos ics, careful routing of power, ground and signals will reduce circuit noise. low average active power cmos technology provides the cy14b101l the benefit of drawing significantly less curren t when it is cycled at times longer than 50 ns. figure 2 shows the relationship between i cc and read/write cycle time. worst-case current consumption is shown for commercial temperature range, v cc = 3.6v, and chip enable at maximum frequency. only standby current is drawn when the chip is disabled. the overall average current drawn by the cy14b101l depends on the following items: 1. the duty cycle of chip enable. 2. the overall cycle rate for accesses. 3. the ratio of reads to writes. 4. the operating temperature. 5. the v cc level. 6. i/o loading. figure 2. current vs. cycle time
advance information cy14b101l document #: 001-06400 rev. *a page 7 of 17 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature .................................. ?65 c to +150 c ambient temperature with power applied............................................. ?55 c to +125 c supply voltage on v cc relative to gnd.......... ?0.5v to 4.1v voltage applied to outputs in high-z state .......................................?0.5v to v cc + 0.5v input voltage ..........................................?0.5v to v cc + 0.5v transient voltage (<20 ns) on any pin to ground potential...................?2.0v to v cc + 2.0v package power dissipation capability (t a = 25c) ................................................... 1.0w surface mount lead soldering temperature (3 seconds) .......................................... +240 c output short circuit current [4] ..................................... 15 ma static discharge voltage......... ........... ............ .......... > 2001v (per mil-std-883, method 3015) latch-up current.................................................... > 200 ma table 2. operating range range ambient temperature v cc commercial 0 c to +70 c 2.7v to 3.6v industrial ?40 c to +85 c 2.7v to 3.6v shaded area contains advance information dc electrical characteristics over the operating range (v cc = 2.7v to 3.6v) [5] parameter description test conditions min. max. unit i cc1 average v cc current t rc = 25 ns t rc = 35 ns t rc = 45 ns dependent on output loading and cycle rate. values obtained without output loads. i out = 0ma. commercial 65 55 50 ma ma ma industrial 70 60 55 ma ma ma i cc2 average v cc current during store all inputs don?t care, v cc = max. average current for duration t store 3ma i cc3 average v cc current at t aa = 200 ns, 3v, 25c typical we > (v cc ? 0.2). all other inputs cycling. dependent on output loading and cycle rate. values obtained without output loads. i out = 0ma. 5ma i cc4 average v cap current during autostore cycle all inputs don?t care, v cc = max. average current for duration t store 3ma i sb v cc standby current we > (v cc ? 0.2). all others v in < 0.2v or > (v cc ? 0.2v). standby current level after nonvolatile cycle is complete. inputs are static. f = 0mhz. 2ma i ix input leakage current v cc = max., v ss < v in < v cc -1 +1 a i oz off-state output leakage current v cc = max., v ss < v in < v cc , ce or oe > v ih -1 +1 a v ih input high voltage 2.2 vcc + 0.3 v v il input low voltage vss - 0.5 0.8 v v oh output high voltage i out = ?2 ma 2.4 v v ol output low voltage i out = 4 ma 0.4 v v cap storage capacitor between v cap pin and v ss , 5v rated 17 57 f table 3. capacitance [6] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 0 to 3.0v 7pf c out output capacitance 7 pf notes: 4. outputs shorted for no more than one second. no more than one output shorted at a time. 5. typical conditions for the active current shown on the front page of the data sheet are average values at 25c (room temperat ure), and v cc = 3v. not 100% tested. 6. these parameters are guaranteed but not tested.
advance information cy14b101l document #: 001-06400 rev. *a page 8 of 17 table 4. thermal resistance [6] parameter description test c onditions 48-ssop 32-soic unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and proce- dures for measuring thermal impedance, per eia / jesd51. tbd tbd c/w jc thermal resistance (junction to case) tbd tbd c/w ac test loads ac test conditions 3.0v output 5 pf r1 577 ? r2 789 ? 3.0v output 30 pf r1 577 ? r2 789 ? for tri-state specs input pulse levels.......................................... 0v to 3v input rise and fall times (10% - 90%)............... < 5ns input and output timing reference levels...........1.5v
advance information cy14b101l document #: 001-06400 rev. *a page 9 of 17 table 5. ac switching characteristics parameters description cy14b101l-25 cy14b101l-35 cy14b101l-45 unit min. max. min. max. min. max. cypress parameter alt. parameter sram read cycle t ace t acs chip enable access time 25 35 45 ns t rc [7] t rc read cycle time 25 35 45 ns t aa [8] t aa address access time 25 35 45 ns t doe t oe output enable to data valid 12 15 20 ns t oha t oh output hold after address change 3 3 3 ns t lzce [9] t lz chip enable to output active 3 3 3 ns t hzce [9] t hz chip disable to output inactive 10 13 15 ns t lzoe [9] t olz output enable to output active 0 0 0 ns t hzoe [9] t ohz output disable to output inactive 10 13 15 ns t pu [6] t pa chip enable to power active 0 0 0 ns t pd [6] t ps chip disable to power standby 25 35 45 ns sram write cycle t wc t wc write cycle time 25 35 45 ns t pwe t wp write pulse width 20 25 30 ns t sce t cw chip enable to end of write 20 25 30 ns t sd t dw data set-up to end of write 10 12 15 ns t hd t dh data hold after end of write 0 0 0 ns t aw t aw address set-up to end of write 20 25 30 ns t sa t as address set-up to start of write 0 0 0 ns t ha t wr address hold after end of write 0 0 0 ns t hzwe [9,10] t wz write enable to output disable 10 13 15 ns t lzwe [9] t ow output active after end of write 3 3 3 ns notes: 7. we must be high during sram read cycles. 8. device is continuously selected with ce and oe both low. 9. measured 200mv from steady state output voltage. 10. if we is low when ce goes low,the outputs remain in the high impedance state
advance information cy14b101l document #: 001-06400 rev. *a page 10 of 17 table 6. autostore/power-up recall parameters description cy14b101l units t hrecall [11] power-up recall duration 20 ms t store [12] store cycle duration 12.5 ms v switch low voltage trigger level 2.55 2.65 v t vccrise vcc rise time 150 s table 7. software controlled store/recall cycle [13,14] parameters description cy14b101l-25 cy14b101l-35 cy14b101l-45 units min. max. min. max. min. max. t rc store/recall initiation cycle time 25 35 45 ns t as address set-up time 0 0 0 ns t cw clock pulse width 20 25 30 ns t glax address hold time 20 20 20 ns t recall recall duration 40 40 40 s table 8. hardware store cycle parameters description cy14b101l units min max t delay [15] time allowed to complete sram cycle 1 s t hlhx hardware store pulse width 15 ns t hlbl hardware store low to store busy 300 ns switching waveforms figure 3. sram read cy cle #1: address controlled [7,8,16] notes: 11. t hrecall starts from the time v cc rises above v switch. 12. if an sram write has not taken place since the last nonvolatile cycle, no store will take place. 13. the software sequence is clocked with ce controlled or oe controlled reads. 14. the six consecutive addr esses must be read in the order listed in the mode selection table. we must be high during a ll six consecutive cycles. 15. read and write cycles in progress before hsb are given this amount of time to complete. 16. hsb must remain high during read and write cycles. t rc t aa t oha
advance information cy14b101l document #: 001-06400 rev. *a page 11 of 17 figure 4. sram read cycle #2: ce and oe controlled [7,16] figure 5. sram write cycle #1: we controlled [16,17] note: 17. ce or we must be > v ih during address transitions. switching waveforms (continued) ce oe t ace t lzce t pu t hzce t doe t lzoe t hzoe t pu ce we t sce t ha t sa t pwe t sd t hd t hzwe t lzwe
advance information cy14b101l document #: 001-06400 rev. *a page 12 of 17 figure 6. sram write cycle #2: ce controlled figure 7. autostor e/power-up recall switching waveforms (continued) ce we t sa t sce t ha t pwe t sd t hd
advance information cy14b101l document #: 001-06400 rev. *a page 13 of 17 figure 8. ce -controlled software store/recall cycle [14] figure 9. oe -controlled software store/recall cycle [14] switching waveforms (continued) t glax ce oe t sa t sce ce oe t sa t sce
advance information cy14b101l document #: 001-06400 rev. *a page 14 of 17 figure 10. hardware store cycle switching waveforms (continued) option: t - tape & reel blank - std. temperature: c - commercial (0 to 70c) i - industrial (?40 to 85c) a - automotive (?40 to 125c) speed: 25 - 25 ns 35 - 35 ns 45 - 45 ns 55 - 55 ns package: sz - 32 soic sp - 48 ssop data bus: k - x8 + rtc l - x8 density: 016 - 16 kb 064 - 64 kb 256 - 256 kb 101 - 1 mb 102 - 2 mb 104 - 4 mb voltage: a - 1.8v b - 3.0v c - 3.3v cypress part numbering nomenclature cy 14 b 101 l - sz 25 c t d - 3.0/3.3v e - 5.0v nvsram 14 - autostore + software store + hardware store 11 - software store 15 - autostore + software store 16 - autostoreplus + hardware store 10 - hardware store 22 - autostore + hardware store 25 - autostore
advance information cy14b101l document #: 001-06400 rev. *a page 15 of 17 ordering information speed (ns) ordering code package diagram package type operating range 25 cy14b101l-sz25ct 51-85127 32-pin soic pb-free commercial cy14b101l-sp25ct 51-85061 48-pin ssop pb-free cy14b101l-sz25it 51-85127 32-pin soic pb-free industrial CY14B101L-SP25It 51-85061 48-pin ssop pb-free cy14b101l-sz25i 51-85127 32-pin soic pb-free CY14B101L-SP25I 51-85061 48-pin ssop pb-free 35 cy14b101l-sz35ct 51-85127 32-pin soic pb-free commercial cy14b101l-sp35ct 51-85061 48-pin ssop pb-free cy14b101l-sz35it 51-85127 32-pin soic pb-free industrial cy14b101l-sp35it 51-85061 48-pin ssop pb-free cy14b101l-sz35i 51-85127 32-pin soic pb-free cy14b101l-sp35i 51-85061 48-pin ssop pb-free shaded areas contain advance information. pl ease contact your local cypress sales representative for availability of these part s. package diagrams pin 1 id seating plane 1 16 17 32 dimensions in inches[mm] min. max. 0.292[7.416] 0.299[7.594] 0.405[10.287] 0.419[10.642] 0.050[1.270] typ. 0.090[2.286] 0.100[2.540] 0.004[0.101] 0.0100[0.254] 0.006[0.152] 0.012[0.304] 0.021[0.533] 0.041[1.041] 0.026[0.660] 0.032[0.812] 0.004[0.101] reference jedec mo-119 part # s32.3 standard pkg. sz32.3 lead free pkg. 0.014[0.355] 0.020[0.508] 0.810[20.574] 0.822[20.878] 32-lead (300-mil) soic (51-85127) 51-85127-*a
advance information cy14b101l document #: 001-06400 rev. *a page 16 of 17 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. autostore and quantumtrap are registered tra demarks of simtek corporation. all products and company names mentioned in this document are the trademarks of their respective holders. package diagrams (continued) 48-lead shrunk small outline package (51-85061) 51-85061-*c
advance information cy14b101l document #: 001-06400 rev. *a page 17 of 17 document history page document title: cy14b101l 1-mbit (128k x 8) nvsram document number: 001-06400 rev. ecn no. issue date orig. of change description of change ** 425138 see ecn tup new data sheet *a 437321 see ecn tup show data sheet on external web

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